1. Field of the Invention
The present invention relates to an IC chip tester and a method for testing an IC chip. More particularly, the present invention relates to an IC chip tester and a method for testing an IC chip, in which test vectors in digital test data are grouped into a plurality of test blocks, and the test data are restored by outputting the test blocks successively.
2. Prior Art
A PCB (Printed Circuit Board) used in electrical appliances has a plurality of IC chips for processing digital signals. The IC chips are connected electrically with each other in the PCB. The connection state and defect of the IC chip are tested by a separate IC chip tester.
Such an IC chip tester inputs test digital signals into the IC chip, and compares the output digital signals of the IC caused by the input signals with predetermined reference signals. The IC chip tester judges normality of the IC chip on the basis of the comparison result.
The IC chip tester inputs test digital signals into the entire PCB, or into a specific digital element in the PCB. In other words according to the object of testing, the test digital signals may be input to the entire PCB or to the specific element in the PCB. The tester for inspecting normality of a specific element is called an In-circuit Tester, and a tester for inspecting the entire PCB or a large block in the PCB is called a Functional Tester.
The recent PCB includes IC chips having high integration degree such as an LSI (large scale integration) and a VLSI (very large scale integration). Such an IC chip has a lot of pins for inputting and outputting digital signals. In order to test such a complex IC chip, very long and complex digital signals as shown in FIG. 1 should be input to the input pins of the IC chips, and such signals are called test data.
One example of the test data is shown in FIG. 2. The test data are also called test pattern, and are expressed by a matrix as shown in FIG. 2. Each of the rows shows data input successively to each of the input pins of the IC chip, and each of the column shows data generated at every clock. Thus, the number of the rows corresponds to the number of input pins of the IC chip, and each of the columns is called test vector. In order to test the IC chip, respective test vectors are successively input to the input pins at every clock.
Most IC chip tester stores the test data into a memory therein, and then generates the test vectors successively at every clock. In general a complex VLSI has hundreds of input and output pins, and the test data comprises thousands of or more test vectors. Accordingly, in order to test a complex IC chip, a memory having a great capacity enough to store a large quantity of test data should be equipped, which causes a voluminous tester and high cost.
In order to overcome such problems, a variety of methods for reducing required capacity of a memory by compressing the test data have been proposed. The compressed test data are stored in the memory, and the compressed test data are converted to the original test data when the IC chip is tested. The IC chip testers necessarily employ a variety of methods for compressing the test data, and the performance and cost of the IC chip tester depend on the efficiency for compressing the test data.
A typical example of the method for compressing the test data is disclosed in U.S. Pat. No. 4,652,814 of Hewlett-Packard. FIG. 3 is a block diagram of the IC chip tester disclosed in U.S. Pat. No. 4,652,814 of Hewlett-Packard. The disclosed Patent employs the method for substituting a part occurring often for a short code, and expresses the entire test data with the substituted codes.
Referring to FIG. 3, test vectors are output from pin driver circuits, and test data are stored in local test data RAMs. The number of pin driver circuits is the same with that of the input pins of the IC chip, and the pin driver circuits are connected to the input pins of the IC chip, respectively. The number of local test data RAMs is also the same with that of the input pins of the IC chip. Thus, the data stored in each of the local test data RAMs correspond to the rows of the test data, and the number of the local test data RAMs is the same with that of the rows of the test data.
In the local test data RAMs, not all the test vectors are stored according to the output order thereof, but one test vector among test vectors identical to each other is stored only one time. Therefore, all of the test vectors stored in the local test data RAMs are different from each other. If one of the test vectors is repeated many times in the test data, that test vector stored in the local test data RAMs is repeatedly utilized. Accordingly, identical test vectors are not repeatedly stored, and thereby the quantity of the entire test data can be greatly reduced.
As such, since only the unique test vectors that are not repeated are stored in the local test data RAMs, an additional device for restoring the test data by combining the test vectors has to be provided. The additional device is called a sequencer.
The sequencer comprises a CPU, a program RAM, a counted/register, a priority encoder, an encoder RAM, and a MUX.
The encoder RAM stores addresses of the respective test vectors stored in the local test data RAMs. A specific test vector in the local test data RAM can be output repeatedly using the addresses.
The counter/register controls encoder RAM through the priority encoder. The counter/register can memorize a specific position of the encoder RAM, and repeatedly use a specific block of the test vectors through the address stored in the encoder RAM. Thus, the counter/register is used when a block consisting of a few test vectors has to be used.
The CPU controls all of the devices in the sequencer. The commands used in the CPU are stored in the program RAM.
A worker stores the test vectors which are not repeated into the local test data RAMs, and stores respective addresses of the test vectors into the encoder RAM. Then, the worker stores the overall control order into the program RAM. Therefore, when the IC chip is tested, the CPU controls the encoder RAM according to the order stored in the program RAM so that the required test vectors are successively output among the test vectors stored in the local test data RAMs. Accordingly, the original test data are restored, and the restored test data are input to the IC chip after being converted by the pin driver circuits to digital signals suitable for the IC chip.
Such an IC chip tester disclosed in Patent of Hewlett-Packard provides an efficient method for compressing the test data, however, there are a few shortcomings as follows.
First, the sequencer has a CPU and thereby the constriction of the sequencer is complex. An additional clock, and ROM and RAM are indispensable for the CPU. Therefore, the whole cost of the IC chip tester increases and the construction thereof becomes complex.
Second, in order to compress the entire test data, the test data should be converted to three types of data required in the local test data RAMs, the encoder RAM, and the program RAM, so the program for converting the test data is complex, and the programming thereof is not easy.